1. Technical Field of the Invention
The present invention relates to a semiconductor device with a multilayer interconnection structure comprising a plurality of wiring layers which are interconnected, between the wiring layers, by via holes provided in an interlayer insulation film.
2. Description of the Related Art
In a semiconductor device with a multilayer interconnection structure, it is necessary to connect a lower-layer wiring and an upper-layer wiring by forming via holes in an interlayer insulation film.
FIG. 1 shows a general via structure of a conventional semiconductor device. Wiring 100 is formed on a lower-layer interlayer insulation film 1. This wiring 100 is composed of a lower barrier metal 2 formed on the interlayer insulation film 1, metal wiring (AlCu) 3 formed on the lower barrier metal 2, and an upper barrier metal 4 formed on the metal wiring 3. The lower barrier metal 2 consists of a Ti layer 2a and a TiN layer 2b. The upper barrier metal 4 consists of a Ti layer 4a and a TiN layer 4b. This wiring 100 is buried in an interlayer insulation film 6 formed on the lower-layer interlayer insulation film 1.
A part of the interlayer insulation film 6 that is directly on the upper barrier metal 4 is removed including a part of the upper barrier metal 4, whereby a via hole is formed. Then, by filling a metal (such as tungsten) in this via hole, a via 5 is formed. The via 5 is connected to wiring (unillustrated) formed on the interlayer insulation film 6.
Here, the following description is given with the lower barrier metal 2 of the metal wiring 100 as being a structure of the TiN layer 2b laminated on the Ti layer 2a, however, as shown in FIG. 2, the lower barrier metal may be a single layer of the TiN layer 2b. 
For the wiring 100 and via 5 of the above-described structure, in a case where wiring (unillustrated) buried in the lower-layer interlayer insulation film 1 directly under the wiring 100 is metal wiring having a large area and in a floating state or the wiring 100 is connected to a large-capacity MOS transistor gate electrode directly or by other wiring, electric charge is easily accumulated in the metal wiring 3, therein exists a problem. In this case, a high resistance layer is easily formed on the surface layer of the upper barrier metal 4 when a via hole is formed in the interlayer insulation film 6. If a high resistance layer is formed on the surface layer of the upper barrier metal 4, conduction between the wiring (unillustrated) formed on the interlayer insulation film 6 and wiring 100 fails.
Since a conduction failure of the via 5 is hardly found by an inspection during manufacturing, it is necessary to prevent this from occurring in the structure.
As a prior art to prevent disconnection at a via-hole portion in a semiconductor device having a multilayer interconnection, one described in Japanese Published Unexamined Patent Application No. H04-38852 exists. For a conventional semiconductor device having multilayer wiring described in this Japanese Published Unexamined Patent Application No. H04-38852, conduction between upper-layer wiring and lower-layer wiring is secured by connecting the upper-layer wiring and lower-layer wiring by a plurality of vias (through-hole portions)
However, the prior art disclosed in Japanese Published Unexamined Patent Application No. H04-38852 is for preventing disconnection caused by a physical force produced by an influence of heat distortion and the like, and no consideration has been given to a conduction failure which is caused by a high resistance layer created at the time of via formation in the above.
Namely, in the above-described prior art, since no measure to suppress creation of a high resistance layer has been taken, even when a plurality of via holes are formed, a high resistance layer may be formed on all thereof to produce a conduction failure.
As such, the conventional semiconductor device with a multilayer interconnection structure has had a problem such that a high resistance layer is created when via holes are formed on metal wiring and this can cause a conduction failure.